1. Field of the Invention
The present invention generally relates to CMOS devices, and more particularly to processing CMOS devices with raised source/drain layers on an ultrathin film SOI.
2. Description of the Related Art
The problems of conventional raised source/drain (RSD) layers with silicon selective epitaxy have been observed during CMOS development. Some solutions such as NiSi formation, which consumes less amounts of silicon, are being developed but have several limitations such as poor thermal stability. Moreover, conventional processing of high-performance CMOS devices with RSD layers on a thin film silicon over insulator (SOI) substrate are subject to the following problems. First, there are challenges of forming an RSD device with silicon selective epitaxy. Conventional processes of RSD involve selective epitaxial growth at high temperatures (typically greater than 825xc2x0 C.) and chemical etch/clean processing during a pre-cleaning process of the doped source/drain (S/D) surfaces. This epitaxial (epi) process is known to be the cause of several technological challenges which hinders the manufacturing of a CMOS device with RSD on an ultrathin SOI. First, the high temperature cycle causes transient enhanced diffusion (TED) of dopants (source/drain extension and halo) that are already introduced in the channel region before the epitaxial step. This is known to induce significant short channel effects such as threshold voltage (Vth) rolloff.
Second, the interface between the epitaxial layer and the existing source/drain regions on the substrate may cause sizable amounts of variability and lack of uniformity of the silicide layer which is formed after the epitaxial process, as well as an increase in S/D resistance. Third, this pre-cleaning process can damage the thin shallow trench isolation (STI) region that is also made of oxide. Fourth, remnants of the epitaxial layer (facets) are formed at the sidewall spacer during the epitaxial process which may contribute to a varying distribution of source/drain dopants that may be implanted after the epitaxial process, thereby negatively impacting device performance. Overall, the conventional epitaxial process involves a complicated surface chemistry in the processing of a CMOS device. Moreover, it has been very difficult to make it viable for CMOS production in the industry.
Therefore, there is a need for a novel CMOS device with raised source/drain layers on an ultrathin film SOI and a method of manufacturing the same, which overcomes the limitations of the conventional processes and structures.
In view of the foregoing, the present invention provides a raised source/drain silicon over insulator transistor device comprising a buried oxide (BOX) layer; a SOI wafer over the BOX layer; a gate dielectric over the SOI wafer; a gate region over the gate dielectric; an implant layer adjacent the SOI wafer, the implant layer comprising a deposited material; source and drain regions above the implant layer and the SOI wafer; and a shallow trench isolation (STI) region adjacent the source/drain region, wherein the STI region has an upper surface that is higher than an upper surface of the gate dielectric. The device further comprises at least one insulating spacer surrounding the gate region. The SOI wafer has a predetermined thickness, and the source/drain region has a thickness greater than the predetermined thickness of the SOI wafer. Moreover, the STI region has a generally rounded corner, wherein the STI region borders the source and drain regions. Furthermore, the dopant layer comprises one of polysilicon and amorphous silicon. Additionally, the source and drain regions are free of epitaxially related defects. In other words, the source and drain regions comprise a non-epitaxial material. Alternatively, an embodiment of the invention provides a CMOS device comprising a buried oxide (BOX) layer; a silicon over insulator (SOI) wafer over the BOX layer, the SOI wafer having a predetermined thickness; a gate structure over the SOI wafer; a gate dielectric between the gate structure and the SOI wafer, the gate dielectric positioned at a first height above the BOX layer; an implant layer adjacent the SOI wafer, the implant layer comprising a deposited material; source and drain regions in the implant layer and the SOI wafer, wherein the source/drain region has a thickness greater than the predetermined thickness of the SOI wafer; and a shallow trench isolation (STI) region having a generally rounded corner and positioned above the BOX layer, wherein an upper surface of the STI region is higher above the BOX layer than the first height. The CMOS device further comprises at least one insulating spacer surrounding the gate structure. The predetermined thickness of the SOI wafer is less than 55 nanometers, and the thickness of the source/drain region is in the range of 200-300 angstroms. Also, the dopant layer comprises one of polysilicon and amorphous silicon.
A method of fabricating a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer; forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and heating the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.
The method further comprises forming at least one insulating spacer surrounding the gate structure. Moreover, the implant layer comprises one of polysilicon and amorphous silicon. Additionally, the gate structure is formed by depositing a first gate polysilicon layer over the SOI wafer; depositing an oxide pad over the first gate polysilicon layer; depositing a sacrificial nitride layer over the oxide pad; and depositing a sacrificial second gate polysilicon layer over the sacrificial nitride layer. The predetermined thickness of the SOI wafer is less than 55 nanometers and the thickness of the source/drain region is in the range of 200-300 angstroms.
The present invention provides a unique solution for a low temperature RSD formation on an ultrathin SOI, gate postdoping, decoupling S/D and polysilicon doping, and gate stack height reduction, all together with high usability and manufacturability. There are several distinguishing features of the present invention over conventional devices and processes. First, the present invention provides a height difference (step) between the STI surface and the gate dielectric interface. Also, according to the present invention, there is the non-existence of several epitaxial-based RSD characteristics, which are inherent in conventional devices, such as facets, polysilicon grains, an interfacial concentration of oxygen, and the lateral overgrowth of selective epitaxy on the polysilicon gate. Moreover, according to the present invention, a non-epitaxial RSD polysilicon layer is globally formed over the STI region and the active areas.
The present invention achieves the following advantages. The present invention resolves all of the basic problems of selective epi-based RSD devices for CMOS on ultrathin SOI by forming RSD without relying on the epi. At the same time the present invention postdopes the polysilicon gate using the polysilicon on the source/drain as a buffer layer. Also, the present invention leads to the reduction of the polysilicon gate height using the same chemical mechanical polish (CMP) for the RSD polysilicon planarization. Furthermore, the present invention achieves RSD on ultrathin SOI with an aggressively scaled conventional gate structure for high performance logic CMOS device fabrication. Moreover, the present invention provides a method of isolating the source/drain electrodes formed by stepped STI and polysilicon etchback using the STI surface as a marker. Additionally, the present invention provides a method to solve problems associated with the polysilicon rail around the step-like corner of STI edge by rounding the corner during pad oxide etching and liner oxidation.